タイトルまたは説明

2 Banks x **2K x *6 Bit Synchronous DRAM Single 3.0V to 3.6V power supply All device pins are compatible with LVTTL interface JEDEC standard **0mil *0pin TSOP-II with 0.8mm of pin pitch All s and outputs referenced to positive edge of system clock Data mask function by UDQM/LDQM Internal two banks operation Auto refresh and self refresh ***6 refresh cycles / *4ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 and Full Page for Sequence Burst - 1, 2, 4 and 8 for Interleave Burst Programmable CAS Latency ; 1, 2, 3 Clocks.