タイトルまたは説明

Features : Clock frequency: **6, **3 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank for hiding row access/precharge Single 3.3V power supply LVTTL interface Programmable burst length (1, 2, 4, 8, full page) Programmable burst sequence: Sequential/Interleave Self refresh modes ***6 refresh cycles every *4 ms Random column address every clock cycle Programmable CAS latency (2, 3 clocks) Burst read/write operations capability Burst termination by burst stop and precharge command Byte controlled by LDQM and UDQM Industrial temperature availability Package: ***-mil **-pin TSOP II Lead-free package is available